The present invention relates to a digital signal processor and, more particularly, to a digital signal processor to which two digital signal series that are expressed by a plurality of bits and have a quadrature phase relation are inputted, and which performs the signal processes relative to the phase information or frequency information.
Due to the remarkable progress of recent integrated circuit technology, the technologies for converting analog signals to digital signals (namely, binary number) and processing the digital signals have been widely used in various fields including electronic communication. The digital signal generated from an A/D converter expresses an amplitude value of the original analog signal by a binary number. A conventional digital signal processor processes such a digital signal indicative of the amplitude value in the format as it is. In a system such as a data modem in the electronic communication field, a number of circuit apparatus such as a phase demodulator or phase synchronous circuit for handling phase information exist. Even in such circuit apparatus which handle the phase information, a conventional digital signal processor processes the digital signal representative of the amplitude value, thereby indirectly handling the phase information. When a practical example is mentioned, the synchronous demodulator for a BPSK (Binary Phase-Shift Keying) signal which is realized by a conventional digital signal processor executes the demodulating operations in accordance with the following procedure. Two digital signal series x and y which have a quadrature phase relation with each other are supplied as input BPSK signals to the demodulator. Further, two digital reference signals which have the quadrature phase relation with each other are also supplied to the synchronous demodulator as reference signals for synchronous demodulation. The two input signal series x and y are expressed as follows. EQU x=cos(.omega..sub.0 t+.theta.) (1) EQU y=sin(.omega..sub.0 t+.theta.) (2)
(where, .theta.=0, .pi.: modulation phase). The two digital reference signals are respectively expressed by cos (.omega..sub.0 t+.phi.) and sin (.omega..sub.0 t+.phi.). The digital values that the input BPSK signals and reference signals take at every moment are amplitude information. A phase comparator provided in the demodulator first performs operations such as EQU xcos (.omega..sub.0 t+.phi.)+ysin(.omega..sub.0 t+.phi.).times.cos(.phi.-.theta. (3) EQU -xsin(.omega..sub.0 t+d)+ycos(.omega..sub.0 t+.phi.).times.sin(.phi.-.theta.) (4)
by three multipliers, one adder and one subtracter. The digital signal expressed in equation (3) is outputted as the demodulation signal. Further, by multiplying those two signals by another multiplier, the digital error signal such as EQU 1/2 sin 2(.phi.-.theta.).times.1/2 sin 2.phi. (5)
is outputted. This error signal corresponds to the phase difference between the carrier phase of the signal series x and y and the phase .phi. of the reference signals irrespective of the modulation phase .theta. of the signal series x and y. This error signal is supplied to a reference signal generator through a loop filter. Thus, the phase of the reference signal is controlled such that the foregoing phase difference becomes zero.
In this way, in the conventional digital demodulator, as shown in equations (1) to (5), the phase difference (.phi.-.theta.) is obtained due to the multiplication, addition and subtraction with respect to the amplitude information using the trigonometric function formulas, thereby generating the error signal. A problem has now arisen since a number of multipliers is needed. Among fundamental operation elements in the digital circuit, the multiplier is the hardware having the largest circuit scale. Therefore, the use of a number of multipliers makes it difficult to realize the digital demodulator by a few LSI (Large Scale Integration) chips. In addition, the use of multipliers is disadvantageous in terms of improvement in processing speed of the digital signal processor.